今日第一階段考試結果9X9

模擬結果圖

模擬程式碼
`define NUM_STATE_BITS 2
`define IDLE 2'b00
`define COMPUTE123 2'b01
`define COMPUTE1234 2'b10
module cl(clk);
parameter TIME_LIMIT = 110000; //1250;
output clk;
reg clk;
initial
clk = 0;
always
#50 clk = ~clk;
always @(posedge clk)
if ($time > TIME_LIMIT) #70 $stop;
endmodule
module slow_div_system(pb,ready,x,y,r3,sysclk);
input pb,x,y,sysclk;
output ready,r3;
wire pb;
wire [11:0] x,y;
reg ready;
reg [11:0] r1,r2,r3;
reg [`NUM_STATE_BITS-1:0] present_state;
always
begin @(posedge sysclk) enter_new_state(`IDLE);
r1 <= @(posedge sysclk) x; r2 <= @(posedge sysclk) y; r3<= @(posedge sysclk) 0; ready = 1; if (pb) begin if (r1 >0)
while (r1 >0)
begin
@(posedge sysclk) enter_new_state(`COMPUTE123);
r1 <= @(posedge sysclk) r1 - 1;
@(posedge sysclk) enter_new_state(`COMPUTE1234);
r3 <= @(posedge sysclk) r2+r3;
end
end
end
task enter_new_state;
input [`NUM_STATE_BITS-1:0] this_state;
begin
present_state = this_state;
#1 ready=0;
end
endtask
always @(posedge sysclk) #20
$display("%d r1=%d r2=%d r3=%d pb=%b ready=%b", $time, r1,r2,r3, pb, ready);
endmodule
module top;
reg pb;
reg [11:0] x,y;
wire [11:0] quotient;
wire ready;
integer s;
wire sysclk;
cl #20000 clock(sysclk);
slow_div_system slow_div_machine(pb,ready,x,y,quotient,sysclk);
initial
begin
pb= 0;
x = 9;
y = 9;
#250;
@(posedge sysclk);
begin
@(posedge sysclk);
pb = 1;
@(posedge sysclk);
pb = 0;
@(posedge sysclk);
wait(ready);
@(posedge sysclk);
if (x/y === quotient)
$display("ok");
else
$display("error x=%d y=%d x/y=%d quotient=%d",x,y,x/y,quotient);
end
$stop;
end
endmodule