第三階段

結果圖:

第二階段

流程圖:

結果圖:

今日第一階段考試結果9X9

模擬結果圖

模擬程式碼
`define NUM_STATE_BITS 2
`define IDLE 2'b00
`define COMPUTE123 2'b01
`define COMPUTE1234 2'b10
module cl(clk);
parameter TIME_LIMIT = 110000; //1250;
output clk;
reg clk;
initial
clk = 0;
always
#50 clk = ~clk;
always @(posedge clk)
if ($time > TIME_LIMIT) #70 $stop;
endmodule
module slow_div_system(pb,ready,x,y,r3,sysclk);
input pb,x,y,sysclk;
output ready,r3;
wire pb;
wire [11:0] x,y;
reg ready;
reg [11:0] r1,r2,r3;
reg [`NUM_STATE_BITS-1:0] present_state;
always
begin @(posedge sysclk) enter_new_state(`IDLE);
r1 <= @(posedge sysclk) x; r2 <= @(posedge sysclk) y; r3<= @(posedge sysclk) 0; ready = 1; if (pb) begin if (r1 >0)
while (r1 >0)
begin
@(posedge sysclk) enter_new_state(`COMPUTE123);
r1 <= @(posedge sysclk) r1 - 1;
@(posedge sysclk) enter_new_state(`COMPUTE1234);
r3 <= @(posedge sysclk) r2+r3;
end
end
end
task enter_new_state;
input [`NUM_STATE_BITS-1:0] this_state;
begin
present_state = this_state;
#1 ready=0;
end
endtask
always @(posedge sysclk) #20
$display("%d r1=%d r2=%d r3=%d pb=%b ready=%b", $time, r1,r2,r3, pb, ready);
endmodule
module top;
reg pb;
reg [11:0] x,y;
wire [11:0] quotient;
wire ready;
integer s;
wire sysclk;
cl #20000 clock(sysclk);
slow_div_system slow_div_machine(pb,ready,x,y,quotient,sysclk);
initial
begin
pb= 0;
x = 9;
y = 9;
#250;
@(posedge sysclk);
begin
@(posedge sysclk);
pb = 1;
@(posedge sysclk);
pb = 0;
@(posedge sysclk);
wait(ready);
@(posedge sysclk);
if (x/y === quotient)
$display("ok");
else
$display("error x=%d y=%d x/y=%d quotient=%d",x,y,x/y,quotient);
end
$stop;
end
endmodule

今日混合式除法機模擬圖和執行畫面

呼... 混合式的乘法機還在努力中 敬請期待>"<

以下是今日混合式除法機執行畫面和結果

第一階段 乘法機完成

第一階段結果圖^^完成

3月12日 紅綠燈挑戰

今日實做程式碼


module top;


reg clk,reset;


wire [1:0]state,speed;


wire [2:0]count;


wire stop;


GYR G1(clk,reset,state,stop,speed,count);


initial


begin


#0 begin reset=1;clk=0; end


#10 reset=0;


#10 clk=1;


repeat(30) #5 clk=~clk;


end


initial


#400 $finish;


endmodule
module GYR(clk,reset,state,stop,speed,count);


parameter GREEN=2'b00,YELLOW=2'b01,RED=2'b10;


input clk,reset;


output [1:0]state,speed;


output [2:0]count;


output stop;


reg [1:0]state,speed,states;


reg [2:0]count;


reg stop;


always@(posedge clk or reset)


begin


if(reset)


begin


states=GREEN;


count=3'b000;


state=0;


stop=0;


speed=2'b11;


end


else


begin


if(states==GREEN && count==3'b000)


begin


state=GREEN;


stop=0;


speed=2'b11;


count=3'b000;


states=YELLOW;


end


else if(states==YELLOW && count==3'b000)


begin


state=YELLOW;


stop=1;


speed=2'b01;


count=3'b000;


states=RED;


end


else if(states==RED && count==3'b000)


begin


state=RED;


stop=1;


speed=2'b00;


count=3'b001;


states=GREEN;


end


else if(states==GREEN && count==3'b001)


begin


state=GREEN;


stop=0;


speed=2'b11;


count=3'b011;


states=YELLOW;


end


else if(states==YELLOW && count==3'b011)


begin


state=YELLOW;


stop=1;


speed=2'b01;


count=3'b011;


states=RED;


end


else if(states==RED && count==3'b011)


begin


state=RED;


stop=1;


speed=2'b00;


count=3'b100;


states=GREEN;


end


else if(states==GREEN && count==3'b100)


begin


state=GREEN;


stop=0;


speed=2'b11;


count=3'b000;


states=YELLOW;


end


end


end


endmodule


模擬結果圖




結果正確成功嚕^^

新學期~

呼 又是新的學期開始嚕!
希望這學期的計算機設計也能順利通過!
加油 加油!